Computers and Technology
8.12 LAB: Toll calculation Toll roads have different fees based on the time of day and on weekends. Write a method calcToll that has three parameters: the current hour of time (int), whether the time is morning (boolean), and whether the day is a weekend (boolean). The method returns the correct toll fee (double), based on the chart below. Weekday Tolls . Before 7:00 am ($1.15) 7:00 am to 9:59 am ($2.95) . 10:00 am to 2:59 pm ($1.90) 3:00 pm to 7:59 pm ($3.95) . Starting 8:00 pm ($1.40) Weekend Tolls Before 7:00 am ($1.05) 7:00 am to 7:59 pm ($2.15) . Starting 8:00 pm ($1.10) Ex: The method calls below, with the given arguments, will return the following toll fees: calctoll(8, true, false) returns 2.95 calcToll(1, false, false) returns 1.90 calcToll(3, false, true) returns 2.15 calcToll(5, true, true) returns 1.05 367608.1813852.qx3207 LAB ACTIVITY 8.12.1: LAB: Toll calculation 0 / 10 LabProgram.java Load default template. 1 public class LabProgram { UWNE public static double calctoll(int hour, boolean isMorning, boolean is Weekend) { /* Type your code here. */ } 5
Design a four-bit shift register (not a universal shift register) with parallel load using D flip-flops. (See Figs. 6.2 and 6.3.) There are two control inputs: shift and load. When shift = 1, the content of the register is shifted toward Az by one position. New data are transferred into the register when load = 1 and shift = 0. If both control inputs are equal to O, the content of the register does not change. A D 4 PC D D D A C Clock Fig. 6.2 Four-bit register with parallel load SI Serial input D D D D so Serial output CLK Fig. 6.3 Four-bit shift register 6.7 Draw the logic diagram of a four-bit register with four D flip-flops and four 4 x 1 mul- tiplexers with mode selection inputs s and . The register operates according to the following function table. (HDL-see Problem 6.35(e), ().) 51 50 Register Operation 0 0 No change Clock Fig. 6.2 Four-bit register with parallel load SI SO Serial input D D D D Serial output CLK Fig. 6.3 Four-bit shift register 6.7 Draw the logic diagram of a four-bit register with four D flip-flops and four 4 x 1 mul- tiplexers with mode selection inputs s and so. The register operates according to the following function table. (HDL-see Problem 6.35(e), (O).) 51 50 0 1 0 1 0 0 1 1 Register Operation No change Complement the four outputs Clear register to 0 (synchronous with the clock) Load parallel data 6.27 Using JK flip-flops: (a) Design a counter with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6. (b) Draw the logic diagram of the counter. 2